Mentor Graphics and TSMC Collaborate to Deliver IC Design and Signoff Infrastructure for 10nm

ILSONVILLE, Oregon, Sept. 27, 2014 /PRNewswire/ — Mentor Graphics Corp. (NA­SDAQ: MENT) today announced that it has entered 10nm collaboration with TSMC. Physical design, analysis, verification and optimization tools have been enhanced to meet 10nm FinFET process requirements for early customers’ test chip and IP design starts.  The infrastructure includes the Olympus-SoC™ digital design system, the Analog FastSPICE (AFS™) Platform including AFS Mega, and the Calibre® signoff solution.

“TSMC and Mentor are doing extensive engineering work that enables mutual customers to take full advantage of advanced process technologies,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Each node requires a tremendous amount of innovations to address new physical challenges, and to increase accuracy for customers’ design enablement, while also providing increased performance and reduced turnaround time.”

Calibre provides the layout pattern’s full-coloring capability to help designers specify color assignments independent of the design cockpit for 10nm rules compliance. For custom layouts, the Calibre RealTime product has been enhanced to enable interactive color checking while designing with all leading custom layout tools, using foundry-certified Calibre signoff decks.

Mentor and TSMC have also enhanced the Calibre fill solution for 10nm FinFET designs. The SmartFill ECO functionality in Calibre YieldEnhancer supports a “fill-as-you-go” flow ensuring that IP and other design blocks are accurately represented as the design progresses. When part of the design is modified, the SmartFill ECO feature can re-fill just the affected portions to minimize turnaround time. Likewise, Calibre LVS has been enhanced to maintain design hierarchy for efficient post-layout simulation at advanced process nodes such as TSMC’s 10nm.

The two companies have also partnered to make the Mentor® Olympus-SoC place and route system ready for TSMC’s 10nm FinFET requirements. Significant enhancements have been made to the database, placement, clock tree synthesis, extraction, optimization and routing engines to make them 10nm FinFET compliant.

To ensure accurate circuit simulation of 10nm FinFET devices, Mentor collaborated with TSMC to validate BSIM-CMG and TMI models for high-speed device and circuit level simulation on the Analog FastSPICE Platform, including AFS Mega. New 10nm FinFET models are also supported by Calibre xACT™ extraction product and the Calibre nmLVS™ product.

Customer successes resulting from the Mentor and TSMC collaborative work on design enablement will be described in sessions at TSMC’s Open Innovation Platform Ecosystem Forum on September 30 at the San Jose Convention Center. For details, refer to the TSMC web site at www.tsmc.com.